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Floating gates !

I'm using SoC Encounter 8.1, with IBM 130nm std cell library. When I submit my layout to foundry it reports (floating gates)...exactly twice the number of std cells used ! So my questions are; do I have to tie the substrate & wells to power pins by hand or it's tied internally in the cell ? And what about ENDCAP cells...can they report such violations if they don't exist ? Note that Encounter reports no errors (there's no Unconnected pins in the design) Thank you

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Amr Zahir over 15 years ago

Thanks Kari Actually I don't have (ENDCAP) or (well tap) cells in my library. I want to know if floating substrate & NWELL can make this (floating gate) violation ?!
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Amr Zahir over 15 years ago

Thanks Kari Actually I don't have (ENDCAP) or (well tap) cells in my library. I want to know if floating substrate & NWELL can make this (floating gate) violation ?!
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