Unplaced IO pins

 Are your IO pads placed yet? Once the IO pads are placed, I believe the pins should be right on top of the IO PAD pins.

 Hi Kari,

I have already placed IO pads. I have a IO assignment file and use the command of loadIoFile to load that file. It works fine. But after that, when I type checkDesign, I still got a number of unplaced pins. I am wondering do I need to write something in IO assignment file for placing pins of top module,

 Thanks 

 Hmmm. It's been a while since I've done a top-level design. Are the number of unplaced pins equal to the number of signal IOs? If you go on through placement and route, do these pins get placed later or do they cause routing issues?

 Those unplaced pins are still there after routing, but I did not get an error for routing. The number of unplaced pins is not equal to the number of signal IOs but the port number of top module, since some ports have more than one bit.Does these unplaced pins really need to be clean out?

Thanks

 If Verify Geometry and Verify Connectivity are clean, and your signoff DRC/LVS are clean, then you're probably fine, but it would always bother me where these things are coming from. The only thing I can suggest is to look at the names of the unplaced pins, see if they make sense in your netlist, or if they should be placed on an IO pad. Maybe these are leftover in a floorplan after the netlist got changed? Are they actual physical shapes, or just logical pin markers? Do they connect to any nets?

 hi  Kari,

I checked the report from checkDesign. All those unplaced IO pins are the pins of top module in the netlist. They have been connected to IO instances directly in the netlist. In PnR view, I saw those pins are bonded with IO instances' pins like PAD. Each of the unplaced pins are just shown as a yellow triangle.

thanks

 I think everything will be fine then. :-)

Hi Kari

 Thank you very much!