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Unplaced IO pins

Greatrebel
Hi All, When I used checkDesign command in Encounter, I found there were a lot of unplaced IO pins. The number of unplaced IO pins is equal to the number of ports in my top-level design. I am wondering how to fix those unplaced IO pins or just leave them alone if it is not a big issue for P&R. Thanks in advanced
Parents

  •  If Verify Geometry and Verify Connectivity are clean, and your signoff DRC/LVS are clean, then you're probably fine, but it would always bother me where these things are coming from. The only thing I can suggest is to look at the names of the unplaced pins, see if they make sense in your netlist, or if they should be placed on an IO pad. Maybe these are leftover in a floorplan after the netlist got changed? Are they actual physical shapes, or just logical pin markers? Do they connect to any nets?

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  •  If Verify Geometry and Verify Connectivity are clean, and your signoff DRC/LVS are clean, then you're probably fine, but it would always bother me where these things are coming from. The only thing I can suggest is to look at the names of the unplaced pins, see if they make sense in your netlist, or if they should be placed on an IO pad. Maybe these are leftover in a floorplan after the netlist got changed? Are they actual physical shapes, or just logical pin markers? Do they connect to any nets?

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