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How to import layout from Virtosuo to Encounter

Greatrebel

Hi All,

We are designing a chip which includes a mixed signal macro. I have the GDS for the MS macro. I am wondering how I can import the layout of the MS macro into our design in Encounter. I load into the gds file during design import, but nothing happens.

Any help will be greatly appreciated.

Thanks in advance

Parents

  •  To include the gds of your macro in the gds output from Encounter, you'll need to use the -merge option of the streamOut command. If the gds from Encounter is what you're sending to the foundry, then you should already be using -merge to get the full layouts of your stdcells and everything else.

    Alternatively, some design flows have all of the stdcell and macro libraries in Virtuoso, and stream the Encounter gds (without the -merge option) into Virtuoso referencing those libraries. Then you stream out the entire design to send to the foundry, and it has all the layout info.

    So you could do either one of these. But a word of caution - make sure that the gds you send to the foundry is the gds that you ran your signoff DRC/LVS on.

    I know you can export LEF from Virtuoso - depending on the complexity of your macro, it may or may not be what you need to generate the LEF. There is an abstract creation tool. Generating .lib is out of my field, I'm afraid. You should post a question to the Custom IC Design forum about the easiest way to get a LEF and .lib of your macro from Virtuoso.

    - Kari

Reply

  •  To include the gds of your macro in the gds output from Encounter, you'll need to use the -merge option of the streamOut command. If the gds from Encounter is what you're sending to the foundry, then you should already be using -merge to get the full layouts of your stdcells and everything else.

    Alternatively, some design flows have all of the stdcell and macro libraries in Virtuoso, and stream the Encounter gds (without the -merge option) into Virtuoso referencing those libraries. Then you stream out the entire design to send to the foundry, and it has all the layout info.

    So you could do either one of these. But a word of caution - make sure that the gds you send to the foundry is the gds that you ran your signoff DRC/LVS on.

    I know you can export LEF from Virtuoso - depending on the complexity of your macro, it may or may not be what you need to generate the LEF. There is an abstract creation tool. Generating .lib is out of my field, I'm afraid. You should post a question to the Custom IC Design forum about the easiest way to get a LEF and .lib of your macro from Virtuoso.

    - Kari

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