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deciding insertion delay and clock skew.

gops

Usually in a clock tree file we need to provide the values of insertion delay and skew values.I have read , that its usually advisable to give 10% of clock period for minimum skew value if the chip is not much big in size and we can go below to 5% as chip size increases.Anyway the skew value is dependent on the technology also.If I make the skew value to a low value it will make my design consume high power, because of the clock  buffers needed to attain the skew value.So someone please throw some ideas how the skew value and insertion delay values can be chosen for a design.

I know the defenitions of both and also I know the skew value can't be more than the clock period.So please give me a clear answer from your experience, How I can decide a safe skew value for the clock which will meet the timing with minimum power consumption.

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  •  This is going to be very design-dependent, so I think the best thing is to do several experiments until you find something you're happy with. For insertion delay, you may also need to make sure it's not bigger than the clock period.  Also, keep in mind that global skew isn't necessarily a target in itself - it's the local skew that matters. You may be able to still make timing with a bigger global skew (which should reduce the insertion delay/buffers). Sorry if this isn't much help - maybe some other users will chime in with some advice!

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  •  This is going to be very design-dependent, so I think the best thing is to do several experiments until you find something you're happy with. For insertion delay, you may also need to make sure it's not bigger than the clock period.  Also, keep in mind that global skew isn't necessarily a target in itself - it's the local skew that matters. You may be able to still make timing with a bigger global skew (which should reduce the insertion delay/buffers). Sorry if this isn't much help - maybe some other users will chime in with some advice!

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