Determining timing margins for a process/design

 I think everyone arrives at it a bit differently. A lot of things can factor in. One thing is clock jitter - if you know how much that is, you want your clock uncertainty to be at least that much. But sometimes you may want to add margin because you're not sure of a library's timing accuracy, or maybe you don't have a library at the exact PVT the design will be running at, etc. There could be many reasons. Before OCV derating was used, margin was added to account for on-chip variation, but now this is handled much better with OCV/derating/CPPR. Some designers may just have a feel for how much setup/hold uncertainty to add for a certain process/library combination. So it really depends on your design and process.

I would love for some other designers to chime in here with any guidelines they have.

 Kari,

Thanks for your inputs.That was helpful.

The other scaling factor normally used in the flow is for RCExtraction. Again this scaling factor could be different for each corner.

Any thoughts/information on arriving at a RC scaling factor?

 Hi Rajesh,

The RC scaling factors are much easier to come by! You can run generateRCFactor (check the text command reference for more details), or you can run ostrich (see the User Guide section "Correlating SPEF Files Using The Ostrich Utility" in the RC Extraction chapter).

- Kari