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Is sign off LVS check neccessary for Encounter based PnR

Greatrebel

 Hi All,

 I would like to ask whether sign off LVS by tools like Assura and Calibre is really neccessary for Encounter based PnR. Because the layout and schematic are all from the layout generated by Encounter. I think ideally they should be same, not like the custom layout design where the schematic and layout are generated seperately by different engineers. And also Encounter does have some basic connectivity check, sign off LVS seems like not that important. Am I right? 

 

Thank you very much

 

 

  • Kari

    I can't stress this enough, you should ALWAYS ALWAYS ALWAYS run signoff DRC and LVS.

    Verify Connectivity is great for finding obvious issues before you go to signoff LVS, but Encounter does not have the full layout, only the metal layers. You can't tape out a design that has not been fully verified. Also, many foundries will run their own DRC before they fab your chip, so if for some reason there was something you didn't see in your own signoff DRC, that serves as a double-check. But it's rare for a foundry to run LVS, so there is no double-check here. YOU MUST RUN SIGNOFF LVS or you are just asking for trouble. :-)

  • Greatrebel

     Hi Kari,

     Thank you very much for your reply. We can not get the spice and gds for std cell, IO cell and so on from the foundry. So I can not have the full layout view when imported into Virtuoso. Is that still meanful to do a sign off LVS without the full layout. And you are right, the foundry does not do sign off LVS for us. They said that " you are able to perform LVS with the phantom views of the standard cells"

     But when I run LVS by Assura, it failed, due to Errors exist in the rules file './extract.rul'. The log file shows there is an unbound value called SCraw. It is the first time I use Assura LVS. I posted this question in another post called "Assura LVS failed by an error in the rule file", but have not gotten any response yet.

     

     

  • Kari

     Hi,

     I saw your Assura post, but unfortunately I don't have any experience with Assura.

    Can the foundry give you more information on running LVS with phantom cells? SOMEONE needs to do a signoff LVS. If the foundry won't give you the layouts, then they should be running the LVS. You can have shorts through the substrate, etc.

    Occasionally we will not be able to get GDS for a macro or something, and we can "black box" that macro. But I have not heard of the case where you can't get the layouts of std cells. I suppose you could black-box everything and just verify the routing. Could you contact your Cadence support AE? Or maybe file a Service Request asking how to run Assura LVS when you don't have cell layouts?

    Sorry I'm not more help.

     - Kari

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