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Is sign off LVS check neccessary for Encounter based PnR

Greatrebel

 Hi All,

 I would like to ask whether sign off LVS by tools like Assura and Calibre is really neccessary for Encounter based PnR. Because the layout and schematic are all from the layout generated by Encounter. I think ideally they should be same, not like the custom layout design where the schematic and layout are generated seperately by different engineers. And also Encounter does have some basic connectivity check, sign off LVS seems like not that important. Am I right? 

 

Thank you very much

 

 

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  • I can't stress this enough, you should ALWAYS ALWAYS ALWAYS run signoff DRC and LVS.

    Verify Connectivity is great for finding obvious issues before you go to signoff LVS, but Encounter does not have the full layout, only the metal layers. You can't tape out a design that has not been fully verified. Also, many foundries will run their own DRC before they fab your chip, so if for some reason there was something you didn't see in your own signoff DRC, that serves as a double-check. But it's rare for a foundry to run LVS, so there is no double-check here. YOU MUST RUN SIGNOFF LVS or you are just asking for trouble. :-)

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  • I can't stress this enough, you should ALWAYS ALWAYS ALWAYS run signoff DRC and LVS.

    Verify Connectivity is great for finding obvious issues before you go to signoff LVS, but Encounter does not have the full layout, only the metal layers. You can't tape out a design that has not been fully verified. Also, many foundries will run their own DRC before they fab your chip, so if for some reason there was something you didn't see in your own signoff DRC, that serves as a double-check. But it's rare for a foundry to run LVS, so there is no double-check here. YOU MUST RUN SIGNOFF LVS or you are just asking for trouble. :-)

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