set_clock_group behavior - SOC81USR3

 Hi,

PLL --(CLK)--------------------------DIVIDER ---(gen_CLK1)---------------------------FLOP_GROUP1

                       |______DIVIDER ---(gen_CLK2)----------------------------FLOPS_GROUP2

I have two generated clocks from master clock CLK as pictured above.

When i define  CLK and gen_CLK2  as asynchronous clock groups i intend not to see timing paths between FLOP_GROUP1 and FLOP_GROUP2. When i load this constraint in encounter i see otherwise.

set_clock_groups -name group1 -asynchronous  -group  [get_clocks {CLK}] -group  [get_clocks {gen_CLK2}]

 I see a timing path between these flop groups clocked by generated clocks reported by encounter.

Is it not implicit that gen_CLK1 and gen_CLK2 are also asynchronous clock groups ?

Is there a switch i should use to see this behaviour with CTE ?

Appreciate your time.

Regards,

Vishnu