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high reg2out

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Dear all

I am working on timing ananlysis for  the first  time. after cts when i check for the setup timings i get the following values.


+--------------------+---------+---------+---------+---------+---------+---------+
|     Setup mode     |   all   | reg2reg | in2reg  | reg2out | in2out  | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
|           WNS (ns):| -4.082  |  0.000  | -0.615  | -4.082  |   N/A   | -0.559  |
|           TNS (ns):| -1135.6 |  0.000  |-121.790 |-997.079 |   N/A   | -16.757 |
|    Violating Paths:|  1107   |    0    |   552   |   468   |   N/A   |   87    |
|          All Paths:|  42404  |  28604  |  16352  |   469   |   N/A   |  1685   |
+--------------------+---------+---------+---------+---------+---------+---------+

I see that the slack for reg2out is high . can some one please tell me how can I reduce. please provilde me some material to read inorder to solve this

Thank u in advance

Suresh


Originally posted in cdnusers.org by suresh235

  • Hi Suresh,

    Some additional questions: what is the step ? preCTS, potsCTS, postRoute ?
    Generally a big violation as your one is a timing constraint problem. You need to check the clocks (the one on the flop and the one on the out). You can also check the output_delay. Very often a big violation is a "false" violation. You can analyse this violation with the file generated by timeDesign (* _reg2out.tarpt).

    Regards ... Luc ...


    Originally posted in cdnusers.org by Black Lutin

  • hello Lutin .

    Thank you for ur reply. the results i had shown above are post CTS values. looks ur right in mentioning abt the timing constriants. I am digging in with the sdc file . I did not get wat u meant by false violation, can u please explain me in detail or can u suggest me some material to read.
    I am also tring to understadn the file reg2out.tarpt.

    Thank your for ur help

    Suresh


    Originally posted in cdnusers.org by suresh235

  • i am attaching a part of the report for reg2out.tar . i can see that for one cell that slew is too large .. any suggestion abt this ?
    ------------------------------------------------------+
    | Cell | Slew | Delay | Arrival | Required |
    | | Time | Time |
    +----------------+-------+-------+---------+----------|
    | | 0.300 | | 1.000 | -5.609 |
    | CKLNQD8 | 0.300 | 0.000 | 1.000 | -5.609 |
    | SDFCNXD | 0.032 | 0.220 | 1.220 | -5.389 |
    |CKND2 | 0.031 | 0.031 | 1.251 | -5.358 |
    | CKND2D | 0.044 | 0.038 | 1.289 | -5.320 |
    | NR2XD | 0.086 | 0.074 | 1.363 | -5.246 |
    | CKND2B | 0.029 | 0.042 | 1.405 | -5.204 |
    || TPND3D | 0.069 | 0.045 | 1.450 | -5.159 |
    | INVD16B | 0.026 | 0.034 | 1.485 | -5.125 |
    | INVD18B | 5.686 | 3.020 | 4.505 | -2.105 |
    | | 8.886 | 3.793 | 8.297 | 1.688 |
    ------------------------------------------------------+


    Originally posted in cdnusers.org by suresh235

  • Which encounter version are you using. I have some problem reading the format.
    Which command did you use for the TA report ? Normally it's timeDesign.

    "false" violations: suppose you hae a clock with a 10 ns period, and a people put 11 ns as an output_delay for a port clocked by this clock. The people make a mistake because it is impossible to achieve the timing.
    This is a "false" violation but a real error in the SDC timing constraints files.

    Regards ... Luc ...


    Originally posted in cdnusers.org by Black Lutin

  • Hello Black Lutun ..

    the problem is solved, it was soem thing todo with sdc ..

    thanks again

    Suresh


    Originally posted in cdnusers.org by suresh235

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