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high reg2out

archive
archive over 17 years ago

Dear all

I am working on timing ananlysis for  the first  time. after cts when i check for the setup timings i get the following values.


+--------------------+---------+---------+---------+---------+---------+---------+
|     Setup mode     |   all   | reg2reg | in2reg  | reg2out | in2out  | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
|           WNS (ns):| -4.082  |  0.000  | -0.615  | -4.082  |   N/A   | -0.559  |
|           TNS (ns):| -1135.6 |  0.000  |-121.790 |-997.079 |   N/A   | -16.757 |
|    Violating Paths:|  1107   |    0    |   552   |   468   |   N/A   |   87    |
|          All Paths:|  42404  |  28604  |  16352  |   469   |   N/A   |  1685   |
+--------------------+---------+---------+---------+---------+---------+---------+

I see that the slack for reg2out is high . can some one please tell me how can I reduce. please provilde me some material to read inorder to solve this

Thank u in advance

Suresh


Originally posted in cdnusers.org by suresh235
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  • archive
    archive over 17 years ago

    Which encounter version are you using. I have some problem reading the format.
    Which command did you use for the TA report ? Normally it's timeDesign.

    "false" violations: suppose you hae a clock with a 10 ns period, and a people put 11 ns as an output_delay for a port clocked by this clock. The people make a mistake because it is impossible to achieve the timing.
    This is a "false" violation but a real error in the SDC timing constraints files.

    Regards ... Luc ...


    Originally posted in cdnusers.org by Black Lutin
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  • archive
    archive over 17 years ago

    Which encounter version are you using. I have some problem reading the format.
    Which command did you use for the TA report ? Normally it's timeDesign.

    "false" violations: suppose you hae a clock with a 10 ns period, and a people put 11 ns as an output_delay for a port clocked by this clock. The people make a mistake because it is impossible to achieve the timing.
    This is a "false" violation but a real error in the SDC timing constraints files.

    Regards ... Luc ...


    Originally posted in cdnusers.org by Black Lutin
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