issues with power routing

I have a design where the std. cells are driven with two different supply voltages,' vdd1' and' vdd2', and a common ground 'gnd'. the gate level verilog netlist doesnt have any reference to these pwr/gnd. Although, my LEF file has it defined in the cell macros as pin vdd1, vdd2 and gnd as inout port with shape abutment and power for (vdd1 and vdd2) and ground for (gnd) with M1 layers. (attached a picture of the LEF file used for the power and gnd) Im using encounter version 9.1, when i have specified, power nets as vdd1 and vdd2, and ground nets as gnd, the issue is when i use SROUTE to route the supply nets and the ground nets, i clearly understands ground and routes it right, but, it SHORTS the other two power supply lines vdd1 and vdd2. and names it as common vdd1. I have tried routing it from command line using sroute -net {vdd1} and sroute -net {vdd2} separately, and that dint help either!..any help will be greatly appreciated. i tried to define it as global net and it still does the same! i have added the supply lines (vdd1, vdd2, gnd) as rings and the supply nets seem to originate at the right point (LHS side of the ring at vdd1 and vdd2 resp.) for vdd1 vdd2 and gnd but when it terminates at the RHS of the power ring, vdd1 and vdd2 terminates either at vdd1 or vdd2 (shorts vdd1 and vdd2).