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issues with power routing

superman321
I have a design where the std. cells are driven with two different supply voltages,' vdd1' and' vdd2', and a common ground 'gnd'. the gate level verilog netlist doesnt have any reference to these pwr/gnd. Although, my LEF file has it defined in the cell macros as pin vdd1, vdd2 and gnd as inout port with shape abutment and power for (vdd1 and vdd2) and ground for (gnd) with M1 layers. (attached a picture of the LEF file used for the power and gnd) Im using encounter version 9.1, when i have specified, power nets as vdd1 and vdd2, and ground nets as gnd, the issue is when i use SROUTE to route the supply nets and the ground nets, i clearly understands ground and routes it right, but, it SHORTS the other two power supply lines vdd1 and vdd2. and names it as common vdd1. I have tried routing it from command line using sroute -net {vdd1} and sroute -net {vdd2} separately, and that dint help either!..any help will be greatly appreciated. i tried to define it as global net and it still does the same! i have added the supply lines (vdd1, vdd2, gnd) as rings and the supply nets seem to originate at the right point (LHS side of the ring at vdd1 and vdd2 resp.) for vdd1 vdd2 and gnd but when it terminates at the RHS of the power ring, vdd1 and vdd2 terminates either at vdd1 or vdd2 (shorts vdd1 and vdd2).
  • superman321
    can anyone tell the difference bwtn the core wire and the follow pin wire, the tool seems to route the vdd1, vdd2 and gnd with follow pin wire and when connecting to core rings, it seems to use 'corewire' for connection, where it shorts the vdd1 and vdd2. here is the picture.
    enc_core_wire_short.pdf
  • Kari

     Can you post a picture of some of the std cells, where the followpins are coming from, so we can see how the two different rails are set up?

  • superman321
    kari, thanks-a-bunch for the reply!.. have been fighting with the tools for weeks now. here is picture of the std cell that im using with two vdd supplies and common gnd!...attached a picture with this post
    enc_pwr_issues.pdf
  • Kari

     I'm sorry you've been fighting with this for so long. In the second picture, the one with the actual power routes, could you zoom out enough to show one of the std cells and how the followpins are starting from there? It kind of looks like the two different pwr lines are overlapping each other. I need to see more of the picture. The LEF looks fine.

  • wally1

    Can you post what you globalNetConnect settings are? I believe they should be:

     

        globalNetConnect VDD1 -type pgpin -pin VDD1 -all

        globalNetConnect VDD2 -type pgpin -pin VDD2 -all

     

    Use the -override switch with globalNetConnect to override the current assignments to see if that helps.

     

  • Kari

     Thanks - I meant to ask about the globalNetConnect as well, and forgot before I hit the Post button.

  • superman321
    thanks for the reply guys!...but, unfortunately, i does the same thing again!...i starts at the correct power core ring on the left-side and when i routes through the core with "follow pin", and when it ends at the core ring on right, it always shorts the vdd1 and vdd2, which ever core ring comes first! Here is the picture!
  • wally1

    If you run VerifyConnectivity and VerifyGeometry does it catch the short? If so, the connectivity is likely defined properly and SRoute is connecting them wrong. If that is the case, please try running the latest release EDI91USR2 (available at http://downloads.cadence.com). If that does not resolve the issue I suggest opening a Service Request at http://support.cadence.com so an AE can assist you further and enter a CCR to get this fixed as needed.

  • superman321
    Thanks for the reply, and YES, its does give me "short violation" of "special net vdd1 and vdd2". I'll try running the newer EDI91USR2 and see if can fix the bug. many thanks for the reply!
  • superman321
    Yes, the connectivity report also has some issues ...reports dangling wire and "open" wire for every power and gnd net SROUTE routes!

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