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issues with power routing

superman321
I have a design where the std. cells are driven with two different supply voltages,' vdd1' and' vdd2', and a common ground 'gnd'. the gate level verilog netlist doesnt have any reference to these pwr/gnd. Although, my LEF file has it defined in the cell macros as pin vdd1, vdd2 and gnd as inout port with shape abutment and power for (vdd1 and vdd2) and ground for (gnd) with M1 layers. (attached a picture of the LEF file used for the power and gnd) Im using encounter version 9.1, when i have specified, power nets as vdd1 and vdd2, and ground nets as gnd, the issue is when i use SROUTE to route the supply nets and the ground nets, i clearly understands ground and routes it right, but, it SHORTS the other two power supply lines vdd1 and vdd2. and names it as common vdd1. I have tried routing it from command line using sroute -net {vdd1} and sroute -net {vdd2} separately, and that dint help either!..any help will be greatly appreciated. i tried to define it as global net and it still does the same! i have added the supply lines (vdd1, vdd2, gnd) as rings and the supply nets seem to originate at the right point (LHS side of the ring at vdd1 and vdd2 resp.) for vdd1 vdd2 and gnd but when it terminates at the RHS of the power ring, vdd1 and vdd2 terminates either at vdd1 or vdd2 (shorts vdd1 and vdd2).
  • Guys, btw, Im using the version EDI9.1USR2. Here are the results from running "encounter -version" @(#)CDS: Encounter v09.12-s159_1 (64bit) 07/15/2010 13:31 (Solaris 5.10) @(#)CDS: NanoRoute v09.12-s013 NR100629-2344/USR64-UB (database version 2.30, 102.1.1) {superthreading v1.15} @(#)CDS: CeltIC v09.12-s012_1 (64bit) 07/01/2010 02:36:14 (SunOS 5.10) @(#)CDS: AAE 09.12-e022 (64bit) 07/15/2010 (SunOS 5.10) @(#)CDS: CTE 09.12-s069_1 (64bit) Jul 15 2010 05:48:15 (SunOS 5.10) @(#)CDS: CPE v09.12-s009 and Im attaching a picture of Geometry and connectivity errors for pwr routing.

  •  First, is there a labelling mistake in your earlier picture? All the rings are labeled VDD1. Also, it doesn't look like things start out correctly either. The VDD1 and VDD2 followpin rails are too close to each other and shorting. Can you try running sroute after you've placed some cells? Maybe having the cells there will help sroute see the two different pwr pin locations.

  • Kari, SORRY abt the earlier picture, yes there are labeling errors, the innermost is the GND, followed by VDD2 and VDD1 in that order. And YES, i have tried, placing the cells and then doing the pwr routing with SROUTE too. It does the same thing again. here is the picture of the left and right side of core rings and the VDD1 and VDD2 are not close to each other, they are abt the min. allowable distance between two metal1 layers!...it looks like they are very close. Attached a picture of the zoomed Pwr lines too!
  • Here is the picture of the power lines, (VDD1 and VDD2) running along the core connecting the core rings!

  •  Thanks for the additional pictures. I see, zoomed out it just looked like they were too close together.

    Check to make sure that your rings are not shorted to each other. Sroute is definitely getting VDD1 and VDD2 confused - maybe because the rings are shorted somewhere. Also, to double-check your global net settings, turn on the Q button at the bottom of the Encounter window, and hover the mouse over the vdd1 and vdd2 pins on one of the std cells. Make sure you see the correct net connection listed in the bottom of the window. 

    You can also try drawing one of the connections by hand and see what happens - sometimes that gives us a clue as to why the tool isn't making the connection.

    If all of this checks out, then it's definitely time for a CCR.

  • Thanks for the reply Kari! I have definitely checked and rechecked, to ensure no shorts of the power rings. also Im posting a picture from design browser, where i think it clearly understands that the std. cells each have two supply lines (VDD1 and VDD2) and common GND. BTW, HOW do i make those manual connection, i looked around in the menu bar. i clearly remember the previous version had the option of manual routing in menu bar.!...AND, the design which im trying to PAR is the same design that worked on the previous encounter version and not in this version (EDI9.1USR2)!!!

  •  The design browser shows that there are VDD1 and VDD2 pins on the cell, but not what they are connected to. Please do the Q/mouse check like I described. Also, please paste your globalNetConnect lines like Wally1 asked. This could help us debug.

  • Kari, I here are the picture doing the "Q" over the power line after using "SROUTE". btw, here are some WARNINGS : "no core cells defined in the COMPONENTS section" and "and/or NO CORE cells defined in special nets VDD1, VDD2 and GND." And, how do i check for globalNetConnect lines that you pointed out in the previous post?

  •  I'd like you to do Q over the pwr pins on the std cells. Turn off the special routes, turn on std cell pins, and do Q over both the VDD1 and VDD2 pins and see what it says.

    For the globalNetConnect, you would have entered these commands yourself, or as part of a script. You can grep your log or command file for globalNetConnect. If you have not set these up, that's likely the problem.

  • Kari, many thanks for the reply. Here are the global setting for the pwr lines: (from log file) globalNetConnect VDD1 -type pgpin -pin VDD1 -inst * -override -verbose globalNetConnect VDD2 -type pgpin -pin VDD2 -inst * -override -verbose globalNetConnect GND -type pgpin -pin GND -inst * -override -verbose btw, the tools does routes the pwr line 'right', if we place the std.cells and then use SROUTE to route the pwr lines!...but, routing the pwr lines and then placing the cells seems to short the two vdd rings!

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