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assign statement check

tiEngr

Hi All,

Is there a way to check en encounter if there is any assign statement present in the DB. Lets assume we didnot use setDoAssign and set rda_Input(assign_buffer)   {1} variable.  I dont see any thing in checkDesign or checkNetlist

Thanks

  • I was searching the Cadence Online Support site (support.cadence.com) and found reportIgnoredNets will output this information. The only caveat is the design must be placed before running this command. Here is the solution:

     

    http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:ViewSolution;solutionNumber=11470268

     

     For example:  reportIgnoredNets -outFile ignored.rpt

     

    The file then contains:

     

    Net Name                          Reason

    a_out                                Assign Net

     

    Hope this helps,

    Brian

  • Thanks Brian, 

    That should work for me. As I was looking to dump out reports after final DB is ready.  Just a sanity check if by accident we let assign statement go and avoid LVS problems later on. 

     

    Thanks,

    Irfan

  • Hi, Assign statements should be removed well before loading the design into database. If at all assign statements are present in the design,we cannot estimate the actual area of the design, second thing is that the tool cannot understand the "assign" and may unable to perform.

  • Does it still hold good for innovus as well? Cant the innovus handle the assign statements as of today?

  • Innovus handles assign statements now. You shouldn't have to do anything special with assigns, unless some other tool in your flow doesn't like them.

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