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  3. Miss VDD pin in LEF file generated with lefout command

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Miss VDD pin in LEF file generated with lefout command

weian
weian over 14 years ago

 I'm doing a bottom-up multi-level hierarchical design.On the first layer, I designed all blocks and use lefout to generate their LEF files. Everything looks fine. On the 2nd layer, I use assembleDesign to put all block designs into one single block. Then I want to use lefout command to generate the LEF file for this single block. Now the problem occurs. The generated LEF only include VSS pin but there's no VDD pin. I check the assembled layout. The VDD power stripes from each blocks are as nice and clear as the VSS stripes. I verified globalNetConnect of both VDD and VSS and couldn't find the reason.

Has anyone seen this problem before? Did I miss something? Thanks very much.

 

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  • Kari
    Kari over 14 years ago

     Can you paste your lefOut command?

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  • weian
    weian over 14 years ago

     This is command I used:

     lefout theCore.lef -specifyToplayer 8 -stripePin -PGpinLayers 7 8

    The power stripes are located only in layer 7 and 8.

     

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  • Kari
    Kari over 14 years ago

     Did you try the following argument to lefOut: (along with what you already have)

    -extractBlockPGPinLayers layer_number_list

     

     

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  • weian
    weian over 14 years ago
    Yes I did. Same result. Only VSS and no VDD. As far as I understand, with "assembleDesign" command, all block layerouts are brought to the current level so the top level should be like a flat design. This makes it even mroe confusing because "lefout" works fine with each blocks which are flat designs themselves. So after I put them together and make the top design flat, the "lefout" command should be working identically. I even used createPGPin to re-create VDD pin. Still failed.
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  • Kari
    Kari over 14 years ago

     You're right, the design is flat once you do assembleDesign. But this assembled design is still a block, is that right? Not a top-level with IO rings or a bump grid?

    Are you sure you don't have a power/ground short somewhere, between the blocks and the top-level? The stripes line up properly?

    After you assemble the design and output a flat DEF, do you see both VSS and VDD in the SPECIALNETS section, and are there routes/stripes in the SPECIALNETS section for each?

    Just throwing out some ideas of things to check, because this should work as expected. You don't need to createPGPin for lefOut -stripePin to work. (But it was a good idea to try that out!)

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  • BobD
    BobD over 14 years ago

    I'm stumped.  I thought it might have something to do with the pwrnet/gndnet specification in one of your .conf files (there would be multiple in an assembleDesign scenario, right?).  Even when I set the rda_Input(ui_pwrnet) variable to "" in the .conf file lefOut still wrote it out.

    I haven't tested after doing an assembleDesign but I can't image how that would foul it up.  If you save/restore after assembleDesign do you see the same result?

    Other than that, I'd suggest you file a service request so that one of our applications engineers can get a testcase from you to pinpoint the cause of the failure.

    Thanks for posting to the forums - sounds like a strange one.

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