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Miss VDD pin in LEF file generated with lefout command

weian

 I'm doing a bottom-up multi-level hierarchical design.On the first layer, I designed all blocks and use lefout to generate their LEF files. Everything looks fine. On the 2nd layer, I use assembleDesign to put all block designs into one single block. Then I want to use lefout command to generate the LEF file for this single block. Now the problem occurs. The generated LEF only include VSS pin but there's no VDD pin. I check the assembled layout. The VDD power stripes from each blocks are as nice and clear as the VSS stripes. I verified globalNetConnect of both VDD and VSS and couldn't find the reason.

Has anyone seen this problem before? Did I miss something? Thanks very much.

 

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