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Danglling wires after LVS

ssuhas over 14 years ago

Hi,

For my block level design I am getting danglling wires after doing verify connectivity.

I am getting these errors at the end of all standard cell rails.

What is the reason for the error and how do we debug it?

Thanks

mikhail over 14 years ago

What do you see on these markers?
Is it opens? It can be caused by missing wires between rings/stripes and std cells rails.
ssuhas said:
What is the reason for the error and how do we debug it?

Please attach a screenshot for one of violations. It will help to debug it.
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diablo over 14 years ago

do you have end cap cells at the end of core rows ?
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ssuhas over 14 years ago

No I dont have any end cap cells at the end of core rows.....
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diablo over 14 years ago

I would suggest adding end cap cells at the end of core rows using
addEndCap
[-help]
-preCap cellName
-postCap cellName
[-prefix prefixName]
[-coreBoundaryOnly]
[-flipY]
[-powerDomain powerDomainName]
[-area x1 y1 x2 y2]
End-cap cells are preplaced physical-only cells that are required to meet certain design rules.
They are placed at the ends of the site rows.
See if it fix your issue.
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Kari over 14 years ago

For a block-level, you can probably ignore these. verConn is just telling you that these rails do not terminate at stripes, and depending on your design, that could be fine. (at the top-level, the rails will continue and end up terminating at stripes or a ring).
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