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Help: SOC Encounter DEFout and Virtuoso DEFin

Ruri

Hi,

I've been doing analog designs, and new to the digital implementation. Really really need your help, these problems have troubled me for several days!

I did the APR in SOC encounter (Ver 9.1), and the results looked OK. So I DEFout (5.5) and DEFin to the Virtuoso (Ver 5141), the VIAs and Standcells are missing, and lots of warning like this:

************************************************************************************************** 

\o Processing VIAS Section

\w *WARNING* dbOpenCellViewByType: Failed to open cellView (VIAGEN12_1 layout) from lib (tsmcN65) in 'r' mode because cellview does not exist.

\w *WARNING* dbOpenCellViewByType: Failed to open cellView (VIAGEN12_3 layout) from lib (tsmcN65) in 'r' mode because cellview does not exist.

\w *WARNING* Unable to find site master CORE.

.........

\o Processing COMPONENTS Section

\w *WARNING* Unable to find master DFCNQD1!

\w *WARNING* Unable to find master DFCNQD1. Instance TMP_REG[0] not created.

.......... 

*****************************************************************************************************************

I googled a lot, and found a post suggested that I might have left out the reference library that contains the VIA information. But what kind of reference library has the VIA information? Right now I only have a standard cell library from TSMC that contains all of the standard cells, with only schematic, symbol and layout view (NO ABSTRACT view!!).

Given I'm only having the standard cell library without abstract view, is it possible to transfer the digital layout to Virtuoso? I need to integrate both the digital and analog layout as a chip.

Really don't know what to do next ... please, help!  

Any comments, suggestions are appreciated!

Parents
  • Ruri
    Thank you, Kari. Don't know what you're trying to say, but I solved the problem. It took me some time to correctly import the verilog netlist with power and ground pins, so that I can proceed the LVS with general analog flow. Thanks, Ruri
Reply
  • Ruri
    Thank you, Kari. Don't know what you're trying to say, but I solved the problem. It took me some time to correctly import the verilog netlist with power and ground pins, so that I can proceed the LVS with general analog flow. Thanks, Ruri
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