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how to do floorplanning for a flip chip

gops

Can some one please share some doc or expalin to me how should I floorplan the IO cells for flipchip and what are the steps involved in flipchip design.Do I require any special tool for IO planning or can I do it in Encounter itself.

 

thanks in advance

gops

  • Kari

     Did you read the "Flip Chip Methodologies" chapter in the EDI User Guide?

  • gops
    Hi Kari,
     
    Thank you for the reply.How are you doing.
     
    I just gone through the doc, but can you please help me for the following queries
     
    1) My LEF don't contain any bump by default.Is it the case of all libraries? Do the foundry need to support for flip chip? I mean is some kind of IO cell needs to be present in my library for doing a flip chip?
     
    2) can you please give me summarized steps( steps are enough).
     
    3) do the bumps have any DRC rules? I don't see any in my design manual or is it enough to take care of the polygon rules of Metals?
     
    4) Is a bump just a single metal or is it a metal array ? can I place a standard cell or macro below the bumps?
     
    I haven't used this IO type before,If you can help i will be so grateful.
     
     
    can you please tell me the library prerequisite required for flip chip .
     
    Thanks
    Gopakumar
  • Kari

     Hi Gops,

     I'm doing well, thanks!

    We usually create the bump lef ourselves. It's pretty simple; you can use a square or an octagon. Here's a quick example for a square bump:

    VERSION 5.6 ;
    BUSBITCHARS "[" ;
    DIVIDERCHAR "/" ;
    UNITS
      DATABASE MICRONS 1000 ;
    END UNITS

    MACRO BUMP
     CLASS COVER BUMP ;
     FOREIGN BUMP -50 -50 ;
     ORIGIN 50 50 ;
     SIZE 100 BY 100 ;
     PIN PAD
        DIRECTION INOUT ;
        USE SIGNAL ;
        PORT
          LAYER M9 ;
            RECT -50 -50 50 50 ;
        END
      END PAD
    END BUMP

    END LIBRARY
     

    A lot of this can depend on your bump gds, technology, etc. but it should be a good starting point.

    Bumps definitely have DRC rules. If they are not in the regular design rule manual, sometimes there is a separate FlipChip design rule manual for your process. Check with your foundry. The foundry definitely needs to support flip-chip for you to do your design and they need to provide you at least the gds for the bump.

     You can think of the bump as a single metal for physical design purposes. In reality, if you look at the layout, you will see different layers included, but these are not layers you would see in EDI. A bump can be placed over std cells, macros, etc. The only exception I can think of right now is that some technologies do not want you to place bumps over RAMs. Again, check with your foundry on this one.

    I'm not exactly sure what kind of steps you're looking for, but a typical flow is like this: the bump grid is defined by the package. You create the bump grid in EDI according to the package, then you know where you need to place the IO cells to best connect to the bumps. You can either use peripheral IO (looks like a wirebond chip, but instead of the IO pads connecting to wires, they route to bumps using the RDL), or areaIO (special IO cells that can be placed anywhere in the chip). "RDL" is an acronymn for "redistribution layer", but all it really means is the very top metal - the same metal that the bump is in. In some cases, the package may not be defined yet, so you have the freedom to assign the bumps however you like.

    Hope that helps,

    - Kari

  • gops
    I have one more doubt regarding the query, Is SOC Encounter tool enough for IO planning and implementation of flip chips or do I need any more tools for IO planning using flip chips?
  • Kari

     You don't need any other tools. EDI can do everything you need.

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