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  3. No connection between VSS/VDD pins and PW ring

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No connection between VSS/VDD pins and PW ring

archive
archive over 17 years ago

I defined power pins and using respective power pading cells. But when I use these commands to connect cell power pin to PW ring and PW ring to VSS and VDD pins, just connections of PW ring and power cell pins were done, no connections between PW ring and VSS/VDD pin (See picture) Somebody can answer me, thank in advance.

### ### first, declare vdd/gnd pin's for all std-cells ### globalNetConnect vdd -type pgpin -pin {vdd } -inst * -module {} globalNetConnect gnd -type pgpin -pin {gnd } -inst * -module {} ### declare 0/1 vhdl/verilog constants to be on vdd/gnd supplys globalNetConnect vdd -type tiehi -module {} globalNetConnect gnd -type tielo -module {} ### ### IO pads ### - All the instance names for the IO pads must have the "io_" prefix ### globalNetConnect vdd -type pgpin -pin {vdd } -inst io* -module {} -override globalNetConnect gnd -type pgpin -pin {gnd } -inst io* -module {} -override

Originally posted in cdnusers.org by thanhtung
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  • archive
    archive over 17 years ago

    Hi,

    I'm not really clear on your question. If you mean you don't see actual routes between the pwr/gnd IO pads and the pwr/gnd ring, then that's because globalNetConnect doesn't actually route the wires. (It just assigns the connectivity.) You need to use Route->Special Route and use the Pad Pins option. Is that your question?

    - Kari


    Originally posted in cdnusers.org by Kari
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  • archive
    archive over 17 years ago

    Hi, I have already corrected this error. Problem did not come from globalNetConnect command, there is a error in LEF file in property descriptions of power padding.

    Anyway thank for your help.


    Originally posted in cdnusers.org by thanhtung
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  • SLTDesigner
    SLTDesigner over 16 years ago

    Hello

    The above comments were very helpful. I have almost the same problem. In perspective, I load a design (in Encounter 5.2 version) and I try to connect the PG nets (for example, VDD and GND) to the pins of the standard cells of the library I am using. The result is that, after doing SRoute, Place, CTS and NanoRoute, the 'Verify Connectiviy' process shows that there are several opens in the special net VDD, therefore it has not at all been correctly routed.

    Could you please help? Thank you very much in advance

    SLTDesigner

     

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  • Kari
    Kari over 16 years ago

     Hi,

     Can you give more details about the Verify Connectivity violations you're seeing? Maybe a picture?

     - Kari

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  • khangupmc
    khangupmc over 15 years ago

     Hello,

    I have exactly the same connectivity problem. 

    Design Name: cordic
    Database Units: 1000
    Design Boundary: (0.0000, 0.0000) (1267.7200, 1267.7200)
    Error Limit = 1000; Warning Limit = 50
    Check all nets
    Net vdd: special open.
    Net gnd: special open.

    Begin Summary
        4 Problem(s) [200]: Special Wires: Pieces of the net are not connected together.
        4 total info(s) created.
    End Summary

     Are you sure that this error comes from LEF? Would you please propose me a solution? Thank you for your help  

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  • Kari
    Kari over 15 years ago

     Again, a picture would really help. Depending on your design, it may or may not be a real issue.

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