No connection between VSS/VDD pins and PW ring

I defined power pins and using respective power pading cells. But when I use these commands to connect cell power pin to PW ring and PW ring to VSS and VDD pins, just connections of PW ring and power cell pins were done, no connections between PW ring and VSS/VDD pin (See picture) Somebody can answer me, thank in advance.

### ### first, declare vdd/gnd pin's for all std-cells ### globalNetConnect vdd -type pgpin -pin {vdd } -inst * -module {} globalNetConnect gnd -type pgpin -pin {gnd } -inst * -module {} ### declare 0/1 vhdl/verilog constants to be on vdd/gnd supplys globalNetConnect vdd -type tiehi -module {} globalNetConnect gnd -type tielo -module {} ### ### IO pads ### - All the instance names for the IO pads must have the "io_" prefix ### globalNetConnect vdd -type pgpin -pin {vdd } -inst io* -module {} -override globalNetConnect gnd -type pgpin -pin {gnd } -inst io* -module {} -override