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no new cells at top level

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I'd like to add no new cells(buffers, inverters...) at top level during timing optimization phase in Encounter. In synopsys flow, I have set compile_no_new_cells_at_top_level as true. Is there any options or variables to do like the above? Thanks in advance.


Originally posted in cdnusers.org by basian2
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  • Hi, I already tried -addPortAsNeeded(-neverAddPort) switch of setOptMode. As you mentioned, it didn't add ports/pins that disturbs hierarchical boundaries of the design. But, a lot of buffer/inverter pairs were still added into the top level hierarchy. I'm looking for another variables/options to prvevent Encounter from add new buffers(inverters) into top level hierarchy during optimization phase. Thanks in advance.


    Originally posted in cdnusers.org by basian2
Reply

  • Hi, I already tried -addPortAsNeeded(-neverAddPort) switch of setOptMode. As you mentioned, it didn't add ports/pins that disturbs hierarchical boundaries of the design. But, a lot of buffer/inverter pairs were still added into the top level hierarchy. I'm looking for another variables/options to prvevent Encounter from add new buffers(inverters) into top level hierarchy during optimization phase. Thanks in advance.


    Originally posted in cdnusers.org by basian2
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