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long wire transition time issues

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In my current design,some wires are quite long,look like over 3000ums,diriven by a buffer,fe does not report the net has transition violation.it should be a problem for the wires are so long.these pins/path are not constrained,could encounter fix this kind thing?if so,what should i do?


Originally posted in cdnusers.org by yhu
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  • You may face such problem if there is no timing path through this net.
    No timing path can come from a false_path, disable_timing_arc or constant propagation from SDC or tie connection coming from the netlist.
    The transition is calculate by the timer, and the consequence is that is there is no path, there is no transition, so no fix on your long wire.
    The trick you can use is to defined a default SDC, where you only put the set_load, set_input_transition ... constrains.
    Load only this new SDC and run optDesign -drv.
    Now the tools should be able to catsh your long net....

    Pat.


    Originally posted in cdnusers.org by bougantp
Reply

  • You may face such problem if there is no timing path through this net.
    No timing path can come from a false_path, disable_timing_arc or constant propagation from SDC or tie connection coming from the netlist.
    The transition is calculate by the timer, and the consequence is that is there is no path, there is no transition, so no fix on your long wire.
    The trick you can use is to defined a default SDC, where you only put the set_load, set_input_transition ... constrains.
    Load only this new SDC and run optDesign -drv.
    Now the tools should be able to catsh your long net....

    Pat.


    Originally posted in cdnusers.org by bougantp
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