Stats

  • Locked Locked
  • Replies 14
  • Subscribers 90
  • Views 18328
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

long wire transition time issues

archive

In my current design,some wires are quite long,look like over 3000ums,diriven by a buffer,fe does not report the net has transition violation.it should be a problem for the wires are so long.these pins/path are not constrained,could encounter fix this kind thing?if so,what should i do?


Originally posted in cdnusers.org by yhu
Parents

  • Hi , Thought the Issues was regarding fixing transition on constant nets , But your Issue was some thing different.
    To address your Issue I need to know the back ground of your environment : like
    What you do is : (and let us know the values too) :
    1. you setAnalysis mode , ( was it set to -setup mode ??)
    2. setExtract mode ( was it -signoff??)
    and also do the below at your end and le me know the results .
    Step-1 : spefIn
    Step-2: selectNet < net with 0ver 3000ums >
    Step-3: reportSelect

    make a note of resistance and cap value on it.

    After doing timeDesign select the same net and do the above Step-1&2 ,

    the whole intention is to know if some thing wrong at yhu end. in doing .

    Once you confirm I will let you know the fixing procedure !! , the mail thing is we need to make to understand that there is a transition violation , if its real .

    cheers,
    -Mohan


    Originally posted in cdnusers.org by mohanch007
Reply

  • Hi , Thought the Issues was regarding fixing transition on constant nets , But your Issue was some thing different.
    To address your Issue I need to know the back ground of your environment : like
    What you do is : (and let us know the values too) :
    1. you setAnalysis mode , ( was it set to -setup mode ??)
    2. setExtract mode ( was it -signoff??)
    and also do the below at your end and le me know the results .
    Step-1 : spefIn
    Step-2: selectNet < net with 0ver 3000ums >
    Step-3: reportSelect

    make a note of resistance and cap value on it.

    After doing timeDesign select the same net and do the above Step-1&2 ,

    the whole intention is to know if some thing wrong at yhu end. in doing .

    Once you confirm I will let you know the fixing procedure !! , the mail thing is we need to make to understand that there is a transition violation , if its real .

    cheers,
    -Mohan


    Originally posted in cdnusers.org by mohanch007
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.