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long wire transition time issues

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In my current design,some wires are quite long,look like over 3000ums,diriven by a buffer,fe does not report the net has transition violation.it should be a problem for the wires are so long.these pins/path are not constrained,could encounter fix this kind thing?if so,what should i do?


Originally posted in cdnusers.org by yhu
Parents

  • Mohan

    As you said, AnalysisMode is set to -checkType setup,and ExtractRCMode -engine signOff

    spefIn and selectNseet and reportSelect before and after timeDesign,R is the same.

    if i set ExtractRCMode -engine detail,and there is a transition violation.

    One thing i need to clarify is that for the current design,no "set_drive_cell" and "set_input_transition" and any constrains like this for the input pins.so what is the default? you know ,set_input_transition 0.6 is ok, but set 0.8 will cause transition violations.

    my think is for such a long wire,directly from input,there should be a problem,so how could encounter handle it?


    Originally posted in cdnusers.org by yhu
Reply

  • Mohan

    As you said, AnalysisMode is set to -checkType setup,and ExtractRCMode -engine signOff

    spefIn and selectNseet and reportSelect before and after timeDesign,R is the same.

    if i set ExtractRCMode -engine detail,and there is a transition violation.

    One thing i need to clarify is that for the current design,no "set_drive_cell" and "set_input_transition" and any constrains like this for the input pins.so what is the default? you know ,set_input_transition 0.6 is ok, but set 0.8 will cause transition violations.

    my think is for such a long wire,directly from input,there should be a problem,so how could encounter handle it?


    Originally posted in cdnusers.org by yhu
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