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Encounter / TimeDesign / ClkGate

Yemelya
------------------------------------------------------------
     optDesign Final Summary                            
------------------------------------------------------------ 
+--------------------+---------+---------+---------+---------+---------+---------+
|     Setup mode     |   all   | reg2reg | in2reg  | reg2out | in2out  | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
|           WNS (ns):| -26.479 | -7.684  | 37.372  | -26.479 | 20.259  |   N/A   |
|           TNS (ns):|-795.285 | -46.559 |  0.000  |-748.726 |  0.000  |   N/A   |
|    Violating Paths:|   150   |    9    |    0    |   141   |    0    |   N/A   |
|          All Paths:|  29196  |  28483  |   798   |   683   |   31    |   N/A   |
+--------------------+---------+---------+---------+---------+---------+---------+  

Hi,What could be a reason for ignoring Clock Gating checks by optDesign and timeDesign?

Thanks a lot.

-Boris 

 

  •  An N/A in the summary table usually means there is something missing in the constraints. Do your clocks actually use clock gating?

  • Thanks Kari!

    Please see below the question I asked at " Logic Design". May be you know an answer.

    _________________

    What is the right way to insert clock gating in RC script?


    I found the following flag:
                   set_attribute lp_insert_clock_gating true

    Is it enough or there is something else needed?

    How should I translate the following instructions from DC for RC:

     set_clock_gating_style -sequential_cell latch \
     -control_point after \
     -control_signal scan_enable \
     -minimum_bitwidth 8 \
     -observation_logic_depth 6

     compile_ultra -gate_clock

    _________________


    Thank you again!

    Boris

     

  •  Hi Boris,

     I'm sorry, but I don't know anything about RC.

    - Kari

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