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Encounter / TimeDesign / ClkGate

Yemelya
------------------------------------------------------------
     optDesign Final Summary                            
------------------------------------------------------------ 
+--------------------+---------+---------+---------+---------+---------+---------+
|     Setup mode     |   all   | reg2reg | in2reg  | reg2out | in2out  | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
|           WNS (ns):| -26.479 | -7.684  | 37.372  | -26.479 | 20.259  |   N/A   |
|           TNS (ns):|-795.285 | -46.559 |  0.000  |-748.726 |  0.000  |   N/A   |
|    Violating Paths:|   150   |    9    |    0    |   141   |    0    |   N/A   |
|          All Paths:|  29196  |  28483  |   798   |   683   |   31    |   N/A   |
+--------------------+---------+---------+---------+---------+---------+---------+  

Hi,What could be a reason for ignoring Clock Gating checks by optDesign and timeDesign?

Thanks a lot.

-Boris 

 

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