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LeafPin usage in CTS

MaK78

Hi,

I have a hierarchical circuit like one shown in attached picture. I would like to stop CTS at "in1" input of module "stage1".
So I added LeafPin definition in my clock specification file.
I tried both:
"LeafPin
+stage1/in1 falling"

and

"LeafPin
+stage1/U1/A falling"

but I received this warning for both:
**WARN: (SOCCK-665): The LeafPin +stage1/in1 falling is an invalid name.
**WARN: (SOCCK-665): The LeafPin +stage1/U1/A falling is an invalid name.

Furthermore it detects clock gating hold violation at U2 in stage2 (attached picture) and adds some buffers in the input of U2 which I wanted to avoid.
I would appreciate if anybody can help me.
by the way, I am using SOC Encounter 8.1.

Thanks in advance.

  •  Please try putting a space after the plus sign "+":

     

    LeafPin

    + stage1/U1/A

     

    otherwise it thinks the + is part of the instance name.

  • Thanks a lot wally1. It works on instance pin :)

    It seems LeafPin doesn't work on hierarchical pins like "+ stage1/in1".

    I have another issue. I have defined both stage1/U1/A and stage2/U2/A as LeafPin (even ExcludedPin) but  "Analyze timing" generates "clock gating hold violation" on pin stage2/U2/A (The other pin of U2 comes from a register) while it shouldn't consider it as a clock anymore.

    Thanks again

  • Does anybody know why network after LeafPin is still checked for clock timing violations (like clock gating hold violation in above example)?

    Thanks in advance.

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