I have a hierarchical circuit like one shown in attached picture. I would like to stop CTS at "in1" input of module "stage1".So I added LeafPin definition in my clock specification file.I tried both:"LeafPin+stage1/in1 falling"
but I received this warning for both:**WARN: (SOCCK-665): The LeafPin +stage1/in1 falling is an invalid name.**WARN: (SOCCK-665): The LeafPin +stage1/U1/A falling is an invalid name.
Furthermore it detects clock gating hold violation at U2 in stage2 (attached picture) and adds some buffers in the input of U2 which I wanted to avoid.I would appreciate if anybody can help me.by the way, I am using SOC Encounter 8.1.
Thanks in advance.
Does anybody know why network after LeafPin is still checked for clock timing violations (like clock gating hold violation in above example)?