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"optDesign -preCTS" doesn't seem to be optimizing

Brannon

I'm trying to get velocity to optimize flop placement at the preCTS stage. The worst path is failing by -504ps, but if I check report_timing on the cycle before and the cycle after the failing path then I see both of these have considerable slack. When I run to later stages it does seem to move those flops around and largely fix the path--but I can't get it to fix those paths at preCTS stage.

I've tried 'optDesign -preCTS -incr', am I on the wrong track here?

  • I usually try "optDesign -preCTS -incr" when it appears placement didn't do a good job sizing/buffering the gates along the worst path. The checking of the cycle before/after the failing path made me think you might be considering useful skew. If you haven't tried that yet you can enable it with "setOptMode -usefulSkew true" prior to optDesign -preCTS. It will attempt to schedule the arrival times of the launch/capture flops to enable timing closure. This information is then conveyed to CTS in a scheduling file.

    If that approach doesn't work well -or- you'd like to improve the placement of this launch/capture flop pair, you might want to try placeDesign -incremental after optDesign -preCTS. I think it would be more likely to move the flops closer together.

    Let us know how it goes!

  •  Thanks for the suggestion--I am indeed just trying to get it to place the flops more optimally (I haven't yet gotten to cycle stealing but that may be my next stop).

    I did an iteration of placeDesign -incremental and that helped but I looked and it still appeared it could do a better job. I did a couple more iterations and the worst path got better each time--but when I look at the worst path it still seemed that it could do much better by simply moving the flop further in one direction (I should mention that this is a wire dominated long route with multiple pipeline stages). I think this is the right track but I need to do more investigation.

    Thanks for pointing me in the right direction.

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