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ncelab: segmentation of a signal

konx

 Hello everyone.

I try to be specific:


- I wrote some Verilog modules for a design (counter, shift registers, etc..)

- Using RTL Compiler I do the synthesis of the design

- I load the desing in Encounter and I do P&R

- Send back the layout to Virtuoso using OpenAccess database

- Encounter produces a post-P&R verilog netlist: saveNetlist name_of_netlist.v -includePowerGround

- Import the post-P&R verilog netlist in Virtuoso using the Import->Verilog option you can find in the Virtuoso menu': this generates the schematic view for all the verilog blocks I wrote for this design

- Run DRC and LVS: during the LVS there is a mistake. One gate (NAND2) is supposed to have input A connected to VDD but Encounter did not make the connection. Ok, I do the connection by hand and LVS is clean.

- Now I want to run AMS-simulations. I setup everything, netlist is ok and compiler is ok, but when I arrive at the Elaboration I receive the following error:

ncelab: *E,CUVNAS (<my_path>/counter_12bit/schematic/verilog.vams,206|19): segmentation of  a signal
.VDD( VDD ), .A( VDD ), .B( reset ) );

Now, this is exactly the port that I connected by hand in Virtuoso and wasn't connected by Encounter (so, I guess there is something related here).

This connection has not been made by me, but it is the result of the synthesized netlist, so I guess that the synthesizer knew what it was doing when it connected the pin A of the NAND2 gate to VDD.

I assume this is some kind of "bug" or something that requires a workaround.

 

Any idea how to solve the problem or where the problem could come from?

 

Thanks

 

Francesco

 

PS: I hope this is the correct forum; sorry for any mistakes

  • Are you using TIEHO and TIELO cells while synthesizing the verilog design? 

  •  

    diablo said:

    Are you using TIEHO and TIELO cells while synthesizing the verilog design? 

     

    Hi diablo,

    we are not using TIEHO and TIELO cells because they are not present in the library we are using. It seems indeed to be problem, but until now the only way to avoid it was to synthesize the design with different constraints, in order not to have such a connection.

    Thanks

     

    Konx

  • Currently, I am also having similar problems. Any input port (not ground port) in standard cell which is tied to VSS instead of TIELO are not being routed by encounter. In my case, they are mostly in scannable flip flops where SI and SE port are unused and tied to VSS instead of TIELO by RTL compiler. I hope other EDI member would shed some light on this issue. 

  • Without tiehi or tielo cells, you need to specify to Encounter what nets to use to connect to instance ports that should be tied to power or ground. Additionally, check that you have defined VDD and VSS as power and ground nets. You do this by using the globalNetConnect commands. Here are the set of commands I run after loading my floorplan:

     

     globalNetConnect VDD -type pgpin -pin VDD -inst * -module {}

     globalNetConnect VSS -type pgpin -pin VSS -inst * -module {}

     globalNetConnect VDD -type tiehi -inst * -module {}

     globalNetConnect VSS -type tielo -inst * -module {}

     applyGlobalNets

  • Thanks Scrivner. I have all those globalNetConnect defined and i do run them after floorplan.

    The problem is with my netlist out of RTL compiler. There were some ports tied to constants and not replaced with tiehi/tielo connection.I am using ' insert_tiehilo_cells -hi TIEHI_A7TULL -lo TIELO_A7TULL', which actually doesn't replace all constants unless I use '-all' switch. Those constants were not recognized by encounter and not routed. However, if i save netlist from encounter those constants 1'b0/1'b1 are replace with VSS/VDD. This causes LVS issue. 

    In my case, i believe the problem will be solved if i make sure there are no constants(1'b0/1'b1) in the netlist out of rtl compiler. This may also be true in your case Knox.

    Thanks 


     

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