ncelab: segmentation of a signal

 Hello everyone.

I try to be specific:

- I wrote some Verilog modules for a design (counter, shift registers, etc..)

- Using RTL Compiler I do the synthesis of the design

- I load the desing in Encounter and I do P&R

- Send back the layout to Virtuoso using OpenAccess database

- Encounter produces a post-P&R verilog netlist: saveNetlist name_of_netlist.v -includePowerGround

- Import the post-P&R verilog netlist in Virtuoso using the Import->Verilog option you can find in the Virtuoso menu': this generates the schematic view for all the verilog blocks I wrote for this design

- Run DRC and LVS: during the LVS there is a mistake. One gate (NAND2) is supposed to have input A connected to VDD but Encounter did not make the connection. Ok, I do the connection by hand and LVS is clean.

- Now I want to run AMS-simulations. I setup everything, netlist is ok and compiler is ok, but when I arrive at the Elaboration I receive the following error:

ncelab: *E,CUVNAS (<my_path>/counter_12bit/schematic/verilog.vams,206|19): segmentation of  a signal
.VDD( VDD ), .A( VDD ), .B( reset ) );

Now, this is exactly the port that I connected by hand in Virtuoso and wasn't connected by Encounter (so, I guess there is something related here).

This connection has not been made by me, but it is the result of the synthesized netlist, so I guess that the synthesizer knew what it was doing when it connected the pin A of the NAND2 gate to VDD.

I assume this is some kind of "bug" or something that requires a workaround.

Any idea how to solve the problem or where the problem could come from?

Thanks

Francesco

PS: I hope this is the correct forum; sorry for any mistakes