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Fixing max transition violation

mwhite

 Hello,

 We get  max transition violations after RC extraction analysis.  They don't show up during P&R optimizations.  All of the violation nets are high buffer nets but not clocks.  One is a reset and the others are not clock or reset.  The violating nets don't necessarily have the highest fanout.

I read in the Forum that it may not be the best to insert high buffer trees on these nets.  What will be the best way to fix this?

Thanks!

Parents

  •  For high-fanout nets like resets, etc. I would definitely recommend building a buffer tree. You can use bufferTreeSynthesis, or add them in to your .ctstch file and have it done along with the clocks. For non-high-fanout transition violations that only show up after extraction (you didn't say if this was signoff extraction vs native), it could be a scale factor issue. Or, you could have some congested areas in the design. During opt, when added buffers are not yet legally placed, the timing is fine - but after a refinePlace, the cell has to be moved far away, resulting in a transition violation. Visually check the net and see if you can tell what's happening.

Reply

  •  For high-fanout nets like resets, etc. I would definitely recommend building a buffer tree. You can use bufferTreeSynthesis, or add them in to your .ctstch file and have it done along with the clocks. For non-high-fanout transition violations that only show up after extraction (you didn't say if this was signoff extraction vs native), it could be a scale factor issue. Or, you could have some congested areas in the design. During opt, when added buffers are not yet legally placed, the timing is fine - but after a refinePlace, the cell has to be moved far away, resulting in a transition violation. Visually check the net and see if you can tell what's happening.

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