Stats

  • Locked Locked
  • Replies 3
  • Subscribers 91
  • Views 19617
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Fixing max transition violation

mwhite

 Hello,

 We get  max transition violations after RC extraction analysis.  They don't show up during P&R optimizations.  All of the violation nets are high buffer nets but not clocks.  One is a reset and the others are not clock or reset.  The violating nets don't necessarily have the highest fanout.

I read in the Forum that it may not be the best to insert high buffer trees on these nets.  What will be the best way to fix this?

Thanks!

Parents

  •  You can try fixing max fanout and see if it helps. Use "setOptMode -fixFanoutLoad true" after adding a max fanout constraint to the SDC file.

    Letting the tool buffer high-fanout nets or building trees for them is a designer preference. Some designs work best with one method, some with the other.

Reply

  •  You can try fixing max fanout and see if it helps. Use "setOptMode -fixFanoutLoad true" after adding a max fanout constraint to the SDC file.

    Letting the tool buffer high-fanout nets or building trees for them is a designer preference. Some designs work best with one method, some with the other.

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.