**ERROR: (ENCCK-216): The number of Clock Gated
components is over 30001. It is not reasonable. Please update you clock
I am getting this error . When i am running CTS in scan mode .How to solve this issue .
I searched for "ENCCK-216" on http://support.cadence.com and found the following solution regarding this message:
Hope this helps you resolve it.
This option mentioned in the solution number 11190368 is not available . setCtsmode -traceMaxGatedCell. Could please suggest me another way of fix it
It is a hidden option. Do you really have over 30,000 clock gating components in your design or is there a problem with the clock tree constraints?