Stats

  • Locked Locked
  • Replies 2
  • Subscribers 90
  • Views 13254
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

timingSelfLoopsNoSkew

Scrivner

Has anyone tried using the  "-timingSelfLoopsNoSkew true" option with setAnalysisMode?

I have a handfull of flops that are showing hold time violations but the timing path on each is between it's own input and output. In the timing report, the clock paths are reported as exactly the same, but the timing on each path is different for some reason.

Encounter documentation for "-timingSelfLoopsNoSkew true" in setAnalysisMode say the option:

"Eliminates clock skew due to clock uncertainty for a path starting and ending at the same register."

But my timing report is exactly the same regardless of whether I set this option to true or false. The hold violation gets flagged either way.

Parents
  • Kari

    Is the clock uncertainty the source of the difference in the path? You could also try:

    set_global timing_cppr_self_loop_mode true


     

Reply
  • Kari

    Is the clock uncertainty the source of the difference in the path? You could also try:

    set_global timing_cppr_self_loop_mode true


     

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.