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timing ECO

nserww

In netlist timing closure period, ASIC designers have to do a lot of timing ECOs 
according to timing violations report file. Timing ECO process is to fix setup or hold timing violations without changing RTL functions. 
It can be inserting buffers inverts or increasing/decreasing cells drive strength or duplicating the heavy fanout cells to off-load fanouts.
But the timing violations report file normally gives hundreds thousands of violated paths and manually fixing even one path takes long time. Making things more complicated is a lot of paths have a lot shared cells in sub-paths.

Does someone who can give me some suggestion or some script??

Thanks a lot! 

Parents
  • After going through a complete flow with EDI (Encounter), you should only be left with a handful of things you need to fix by hand (unless there are other design issues going on). Can you give a few more details about your flow? 
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  • After going through a complete flow with EDI (Encounter), you should only be left with a handful of things you need to fix by hand (unless there are other design issues going on). Can you give a few more details about your flow? 
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