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timing ECO

nserww

In netlist timing closure period, ASIC designers have to do a lot of timing ECOs 
according to timing violations report file. Timing ECO process is to fix setup or hold timing violations without changing RTL functions. 
It can be inserting buffers inverts or increasing/decreasing cells drive strength or duplicating the heavy fanout cells to off-load fanouts.
But the timing violations report file normally gives hundreds thousands of violated paths and manually fixing even one path takes long time. Making things more complicated is a lot of paths have a lot shared cells in sub-paths.

Does someone who can give me some suggestion or some script??

Thanks a lot! 

  • After going through a complete flow with EDI (Encounter), you should only be left with a handful of things you need to fix by hand (unless there are other design issues going on). Can you give a few more details about your flow? 

  • Hi Kari: 

    Thanks for your attention! 

    After going through the flow with EDI ，Prime Time checked still 80 setup violations.In this case,do you think some flow is abnormal? 

     But I used the whole flow which mentioned in the spec.

    In this morning ,i write a script to extract the cells blocking in the PT,and upsize it in encounter.It's nausea and i dont think it is a good resolution.Can u give some suggestion? 

     

     

  • BTW,thanks a lot for your Five-Minute Tutorial.

  • You're welcome, I'm glad you're finding the tutorials useful!

    As for your timing closure, did EDI think the timing was clean, but PT saw 80 violations? You would have to go through some work to correlate the two different tools. This is always a painful exercise, and it may never be exact, but you should be able to get pretty close. How large are the setup violations? Did you see them in EDI? If EDI sees these violations, there is probably some more work that it can do to fix them. Again, it's hard to tell without knowing your design and specific flow.

  • Hi Kari:

    My case is :EDI thought the timing was clean, but PT saw 80 violations.The classical setup violation is 0.15ns.(2 million gates 0.18um)

    My flow is also old ways : 1 Floorplanning and Initial Placement. 2 Placement Optimization.3 Pre-CTS Optimization. 4 Clock Tree Synthesis

    5 Post-CTS Optimization. 6 Detailed Routing. 7 Post-Route Optimization.8 Stream out.

    My SDC file is relax  step by step after cts and DetailRoute,when doing PT,use the most loosen SDC file.

  • There's some kind of correlation issue going on. I don't use PT, so I'm sorry but I won't be much help there. You could leave the SDC constraints a bit tighter in EDI, to make up for the mismatch you're seeing in the end. It's not the ideal solution, but it should work or at least get you closer.

    You could report out the exact same path in EDI and PT, and compare the numbers line-by-line to try to figure out where the mismatch is happening. There may be some timing variables you could set in either or both tools to get a closer match. 

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