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timing ECO

nserww

In netlist timing closure period, ASIC designers have to do a lot of timing ECOs 
according to timing violations report file. Timing ECO process is to fix setup or hold timing violations without changing RTL functions. 
It can be inserting buffers inverts or increasing/decreasing cells drive strength or duplicating the heavy fanout cells to off-load fanouts.
But the timing violations report file normally gives hundreds thousands of violated paths and manually fixing even one path takes long time. Making things more complicated is a lot of paths have a lot shared cells in sub-paths.

Does someone who can give me some suggestion or some script??

Thanks a lot! 

Parents

  • There's some kind of correlation issue going on. I don't use PT, so I'm sorry but I won't be much help there. You could leave the SDC constraints a bit tighter in EDI, to make up for the mismatch you're seeing in the end. It's not the ideal solution, but it should work or at least get you closer.

    You could report out the exact same path in EDI and PT, and compare the numbers line-by-line to try to figure out where the mismatch is happening. There may be some timing variables you could set in either or both tools to get a closer match. 

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  • There's some kind of correlation issue going on. I don't use PT, so I'm sorry but I won't be much help there. You could leave the SDC constraints a bit tighter in EDI, to make up for the mismatch you're seeing in the end. It's not the ideal solution, but it should work or at least get you closer.

    You could report out the exact same path in EDI and PT, and compare the numbers line-by-line to try to figure out where the mismatch is happening. There may be some timing variables you could set in either or both tools to get a closer match. 

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