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timing ECO

nserww

In netlist timing closure period, ASIC designers have to do a lot of timing ECOs 
according to timing violations report file. Timing ECO process is to fix setup or hold timing violations without changing RTL functions. 
It can be inserting buffers inverts or increasing/decreasing cells drive strength or duplicating the heavy fanout cells to off-load fanouts.
But the timing violations report file normally gives hundreds thousands of violated paths and manually fixing even one path takes long time. Making things more complicated is a lot of paths have a lot shared cells in sub-paths.

Does someone who can give me some suggestion or some script??

Thanks a lot! 

Parents

  • Hi Kari: 

    Thanks for your attention! 

    After going through the flow with EDI ，Prime Time checked still 80 setup violations.In this case,do you think some flow is abnormal? 

     But I used the whole flow which mentioned in the spec.

    In this morning ,i write a script to extract the cells blocking in the PT,and upsize it in encounter.It's nausea and i dont think it is a good resolution.Can u give some suggestion? 

     

     

Reply

  • Hi Kari: 

    Thanks for your attention! 

    After going through the flow with EDI ，Prime Time checked still 80 setup violations.In this case,do you think some flow is abnormal? 

     But I used the whole flow which mentioned in the spec.

    In this morning ,i write a script to extract the cells blocking in the PT,and upsize it in encounter.It's nausea and i dont think it is a good resolution.Can u give some suggestion? 

     

     

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