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density increase by 15% after postcts hold optimization

jabbar

Hi,

I'm having problem with the high increase of utilization (from 70% to 85%) when I run optdesign -postcts -hold command in soc encounter. Could anyone please let me know what would be the reason of such dramatic increase of the number of buffer to fix hold violation?

My input delay constraint is about 15% (0.5 ns) of the clock period (3 ns). 

Thanks in advance.

 

 

Parents

  • Please look into your clock tree insertion delay. If it is a large number, then, your input-to-register hold violation fixes will need to add a lot of buffers/inverters (see the in2reg.tarpt for details).  Secondarily, if there is clock skew, then, hold violation will be large between those registers with clock skew and need a lot of buffers/inverters to fix those violations.

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  • Please look into your clock tree insertion delay. If it is a large number, then, your input-to-register hold violation fixes will need to add a lot of buffers/inverters (see the in2reg.tarpt for details).  Secondarily, if there is clock skew, then, hold violation will be large between those registers with clock skew and need a lot of buffers/inverters to fix those violations.

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