density increase by 15% after postcts hold optimization

Please look into your clock tree insertion delay. If it is a large number, then, your input-to-register hold violation fixes will need to add a lot of buffers/inverters (see the in2reg.tarpt for details).  Secondarily, if there is clock skew, then, hold violation will be large between those registers with clock skew and need a lot of buffers/inverters to fix those violations.

These are good suggestions from Tongju.

Additionally in my experience the primary cause of area explosion during hold fixing is a larger than intended hold uncertainty. Check your postcts SDCs and compare the hold uncertainty to what the signoff requirement is for hold uncertainty. Having a hold uncertainty target that's larger than the signoff target is more impactful on the hold side than the setup side because each 10ps (or so) of hold margin can lead to thousands of hold violations which can lead to thousands of delay cells which can lead to area explosion like you see.

Hold SDCs are often not as well vetted during synthesis as compared to setup SDCs so it's particularly common that these things pop up postCTS when hold timing is evaluated for the first time.

To gain further clarity into the types of hold violations that exist, I'd recommend using Encounter's Global Timing Debug feature on the design right after CTS. It will show you a histogram of the hold violations and allow you to categorize them by type which usually illuminates the primary cause of your problems.

Great question - I'd be interested in hearing what you find!

Thank you Tongju and BobD for the suggestions. I have solved it by analyzing the violated paths through "timing analyzer path" from global timing debug menu (setup check). Then I modified my constraints (SDC) and repeat the synthesis and place and route without any significant increase of density after optdesign -postcts -hold command. There is no problem with the clock tree, it is the problem of my constraints, specifically IO constraints.

Can you please tell me how can I view histogram of hold time using timing debug in encounter. I have gone through the timing debug chapter in SOC guide but still dont know how to do that. I tried such as follows:

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create_path_category -name {test} -comment {}

-check_type {{Hold Check}}

-from_port all_inputs

-to_cell all_registers

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but the encounter gives this info:

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INFO(create_path_category) : no paths met the criteria defined for group "test", so the group was not created.

Thanks again.