Can we use VDD and VSS in place of TIE-HI and TIE-LO cells as they are logically equal .
Don't some vendors allow direct VDD/VSS connections?
I'm not a layout guy, so I'm not sure how this is handled electrically (diodes, caps, etc.) but I've seen it before. Maybe some vendors allow but risk the noise issue?
Whether this is appicable for 90nm and 130 nm also or we are using its for 65, 45 or 28nm only .
We ever had this kind of direct connection in our 0.18um chips.