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Encounter Special Route fails (warning ENCSR-1254)

bjbit

Hi,

I am new to P&R on Encounter. When I follow the step to Special Route, it shows the following warning and fails to route.

=========================================================== 

 Begin power routing ...

**WARN: (ENCSR-1254):   Net VDD does not have block pins to be routed. Please check net list.

**WARN: (ENCSR-1255):   Net VDD does not have pad pins to create pad ring. Please check net list or port class. (must NOT be CORE class and must not be AREAIO subclass). 

**WARN: (ENCSR-1256):   Net VDD does not have CORE class pad pins to be routed.

        Please check net list or port class.

Net VDD does not have AREAIO class pad pins to be routed.

        Please check net list or port class.

**WARN: (ENCSR-1254):   Net VSS does not have block pins to be routed. Please check net list.

**WARN: (ENCSR-1255):   Net VSS does not have pad pins to create pad ring. Please check net list or port class. (must NOT be CORE class and must not be AREAIO subclass). 

**WARN: (ENCSR-1256):   Net VSS does not have CORE class pad pins to be routed.

        Please check net list or port class.

Net VSS does not have AREAIO class pad pins to be routed.

        Please check net list or port class.

  Number of IO ports routed: 0

  Number of Block ports routed: 0

   Number of Stripe ports routed: 0

  Number of Core ports routed: 0

  Number of Pad ports routed: 0

  Number of Power Bump ports routed: 0

====================================================
 
My netlist in verilog is:
=====================================================
module PRtest ( out, in );
output  out;
input  in;
NOT I0 ( net1, VSS, in, VDD);
NAND2 I1 ( net3, VSS, net1, net1, VDD);
NAND3 I2 ( out, VSS, net3, net3, net3, VDD);
endmodule

module NOT ( OUT, VSS, IN, VDD );
output  OUT, VSS;
input  IN, VDD;
endmodule

module NAND2 ( OUT, VSS, IN1, IN2, VDD );
output  OUT, VSS;
input  IN1, IN2, VDD;
endmodule

module NAND3 ( OUT, VSS, IN1, IN2, IN3, VDD );
output  OUT, VSS;
input  IN1, IN2, IN3, VDD;
endmodule
================================================= 
 
Since there is not troubleshooting information in user manual or help library, I wish I can find some helps here. Thanks in advance. 

  • This means you turned on the options to route Block pins, pad pads and pad rings but no such pins seem to exist in the design. If the design is purely standard cells then you can disable these options and the warning will not be reported.For standard cells make sure you enable the option for Follow Pins. This option connects the power pins of the standard cells together. 

    Brian

  • Hi Brian,

    Thanks a lot for your advice. Yes I have only 3 standard cells. By disabling other pin options, no more warning is reported. However, still no route generated.

    ==============================

    Begin power routing ...

    Number of Stripe ports routed: 0

    Number of Core ports routed: 0

    ==============================

    My Sroute setting is:

    ==============================

    Begin option processing ...

    (from .sroute_15140.conf) srouteConnectPowerBump set to false

    (from .sroute_15140.conf) routeSelectNet set to "VSS VDD"

    (from .sroute_15140.conf) routeSpecial set to true

    (from .sroute_15140.conf) srouteConnectBlockPin set to false

    (from .sroute_15140.conf) srouteConnectPadPin set to false

    (from .sroute_15140.conf) srouteCrossoverViaTopLayer set to 6

    (from .sroute_15140.conf) srouteFollowCorePinEnd set to 3

    (from .sroute_15140.conf) srouteJogControl set to "preferWithChanges differentLayer"

    (from .sroute_15140.conf) sroutePadPinAllPorts set to true

    (from .sroute_15140.conf) sroutePreserveExistingRoutes set to true

    (from .sroute_15140.conf) srouteTopLayerLimit set to 6

    (from .sroute_15140.conf) srouteTopTargetLayerLimit set to 6

    End option processing

     ================================

    Any further advices for this problem? Thanks again.

  • Try running the following prior to Special Route to define the logical connectivity of the power:

    globalNetConnect VDD -type pgpin -pin VDD -all

    globalNetConnect VSS -type pgpin -pin VSS -all

    Also, make sure the power and ground pins are defined with USE POWER and USE GROUND in the LEF file.

    Brian

  • I'm sorry Brian. But after adding global nets connections, nothing changed. I also double-checked my .lef, as you see:

    ============================

     PIN VDD

        DIRECTION INOUT ;

        USE POWER ;

        PORT

          LAYER M1 ;

            RECT 0.68 0.45 0.92 51.32 ;

            RECT 0.26 50.94 1.2 51.32 ;

        END

      END VDD

      PIN VSS

        DIRECTION INOUT ;

        USE GROUND ;

        PORT

          LAYER M1 ;

            RECT 0.68 -31.91 0.92 -0.71 ;

            RECT 0.68 -31.91 1.54 -31.67 ;

        END

      END VSS

    ================================

    I attached my full .lef file in case you may find something wrong? Thanks for your time and helps. 

  • Your power pins should span the width of the cell. Also, your cells should be the same height or multiples of each other so the power rails align.

  • Thank you, Brian. I will redraw cell layouts later and see if can solve the issue. 

    Futhermore, if you don't mind, may I ask another question here? I tried that ignore Sroute and place standard cells, and then went for Nonoroute. An error shows:

    ======================

     #ERROR (NRDB-158) There is no default via from LAYER M1 to LAYER M2 in RULE LEF_DEFAULT.

    ======================

    However, all via layers should been defined in LEF already.

    ======================

     VIARULE M1_M2 GENERATE DEFAULT

      LAYER M1 ;

        ENCLOSURE -0.02 -0.02 ;

      LAYER M2 ;

        ENCLOSURE 0 0 ;

      LAYER V1 ;

        RECT -0.14 -0.14 0.14 0.14 ;

        SPACING 0.56 BY 0.56 ;

        RESISTANCE 5.000000 ;

    END M1_M2

    ======================== 

  • You need to run the generateVias command before NanoRoute. generateVias will generate the optimal vias based on the VIARULE you defined.

    Brian

  • I am on vacations so might not be able to respond timely. I will get back to work from 2nd Sept, 2012.


    Ciao!

    Affaq Qamar
    Mob:+3280294862
  • Hi Brian, both of my problems are solved. Now I can keep going on. Thanks a ton for your helps.
  • I am on vacations so might not be able to respond timely. I will get back to work from 2nd Sept, 2012.


    Ciao!

    Affaq Qamar
    Mob:+3280294862

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