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Encounter Special Route fails (warning ENCSR-1254)

bjbit

Hi,

I am new to P&R on Encounter. When I follow the step to Special Route, it shows the following warning and fails to route.

=========================================================== 

 Begin power routing ...

**WARN: (ENCSR-1254):   Net VDD does not have block pins to be routed. Please check net list.

**WARN: (ENCSR-1255):   Net VDD does not have pad pins to create pad ring. Please check net list or port class. (must NOT be CORE class and must not be AREAIO subclass). 

**WARN: (ENCSR-1256):   Net VDD does not have CORE class pad pins to be routed.

        Please check net list or port class.

Net VDD does not have AREAIO class pad pins to be routed.

        Please check net list or port class.

**WARN: (ENCSR-1254):   Net VSS does not have block pins to be routed. Please check net list.

**WARN: (ENCSR-1255):   Net VSS does not have pad pins to create pad ring. Please check net list or port class. (must NOT be CORE class and must not be AREAIO subclass). 

**WARN: (ENCSR-1256):   Net VSS does not have CORE class pad pins to be routed.

        Please check net list or port class.

Net VSS does not have AREAIO class pad pins to be routed.

        Please check net list or port class.

  Number of IO ports routed: 0

  Number of Block ports routed: 0

   Number of Stripe ports routed: 0

  Number of Core ports routed: 0

  Number of Pad ports routed: 0

  Number of Power Bump ports routed: 0

====================================================
 
My netlist in verilog is:
=====================================================
module PRtest ( out, in );
output  out;
input  in;
NOT I0 ( net1, VSS, in, VDD);
NAND2 I1 ( net3, VSS, net1, net1, VDD);
NAND3 I2 ( out, VSS, net3, net3, net3, VDD);
endmodule

module NOT ( OUT, VSS, IN, VDD );
output  OUT, VSS;
input  IN, VDD;
endmodule

module NAND2 ( OUT, VSS, IN1, IN2, VDD );
output  OUT, VSS;
input  IN1, IN2, VDD;
endmodule

module NAND3 ( OUT, VSS, IN1, IN2, IN3, VDD );
output  OUT, VSS;
input  IN1, IN2, IN3, VDD;
endmodule
================================================= 
 
Since there is not troubleshooting information in user manual or help library, I wish I can find some helps here. Thanks in advance. 
Parents

  • Thank you, Brian. I will redraw cell layouts later and see if can solve the issue. 

    Futhermore, if you don't mind, may I ask another question here? I tried that ignore Sroute and place standard cells, and then went for Nonoroute. An error shows:

    ======================

     #ERROR (NRDB-158) There is no default via from LAYER M1 to LAYER M2 in RULE LEF_DEFAULT.

    ======================

    However, all via layers should been defined in LEF already.

    ======================

     VIARULE M1_M2 GENERATE DEFAULT

      LAYER M1 ;

        ENCLOSURE -0.02 -0.02 ;

      LAYER M2 ;

        ENCLOSURE 0 0 ;

      LAYER V1 ;

        RECT -0.14 -0.14 0.14 0.14 ;

        SPACING 0.56 BY 0.56 ;

        RESISTANCE 5.000000 ;

    END M1_M2

    ======================== 

Reply

  • Thank you, Brian. I will redraw cell layouts later and see if can solve the issue. 

    Futhermore, if you don't mind, may I ask another question here? I tried that ignore Sroute and place standard cells, and then went for Nonoroute. An error shows:

    ======================

     #ERROR (NRDB-158) There is no default via from LAYER M1 to LAYER M2 in RULE LEF_DEFAULT.

    ======================

    However, all via layers should been defined in LEF already.

    ======================

     VIARULE M1_M2 GENERATE DEFAULT

      LAYER M1 ;

        ENCLOSURE -0.02 -0.02 ;

      LAYER M2 ;

        ENCLOSURE 0 0 ;

      LAYER V1 ;

        RECT -0.14 -0.14 0.14 0.14 ;

        SPACING 0.56 BY 0.56 ;

        RESISTANCE 5.000000 ;

    END M1_M2

    ======================== 

Children
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