I have a problem generating SDF file in encounter. The problem is that the generated SDF file only includes delay information for the interconnects but not the gates. Here is how I generated the SDF file:
I have a standard cell library containing all the required cellviews (i.e. schematic, symbol, layout, abstract), Also I have the LEF file for the mentioned standard cell library. I imported a verilog netlist beside the LEF file in encounter, placed & routed the design, and finally generated the SDF file.
After opening the SDF in an editor I only see delay information for the interconnects. I don't understand why the gates input to output path delays are missing in the generated SDF file.
I would appreciate if somebody could tell me what I'm missing.
Did you import a timing library (Liberty .lib) into Encounter? A timing library is required to define the input to output timing arcs.
Thanks Brian for responding. I did not add the timing libraries because as far as I know these timing libraries are not derived from the extracted layout of the gates, therefore, their timings are not very accurate. I want encounter to use the layout of my cells to generate the timing arcs in the SDF file rather than copying them from .lib files. Does that make sense or I am thinking incorrectly?
Library characterization is beyond what physical design tools like Encounter are designed for. It requires a library characterization tool like Cadence Library Characterization which analyzes the cell for different input slews and output loads to create the characterization.
Encounter allows you to view the layout of the cell but it's the abstract view that is used for place & route.
Alright, then based on what you say, in order to add the timing information of the gates to the SDF file I have to do the following (please correct me if I'm making a mistake) :
- manually extract the RC parasitics of each cell in the library and save it as a netlist
- use a library characterization tool to create a .lib file for the saved netlists
- import the created .lib file beside the verilog and LEF files to encounter
- place & route and generate the SDF file
I checked with one of our library characterization tool experts and here is what I found out for you. Hope this helps.
To create a Liberty timing library characterization needs - 1. Transistor level netlist for the cell (Spice netlist)2. Transistor models (Spice model)3. A command file that tells the tool (ELC, Liberate) what and how to characterize. E.g., what circuit simulator you want to use (e.g., Hspice, Spectre), what timing and cap index etc. The Cadence library characterizer can be Encounter Library Characterizer (ELC) or Liberate.