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SDF generation in Encounter

01farhad10

I have a problem generating SDF file in encounter. The problem is that the generated SDF file only includes delay information for the interconnects but not the gates. Here is how I generated the SDF file:

I have a standard cell library containing all the required cellviews (i.e. schematic, symbol, layout, abstract), Also I have the LEF file for the mentioned standard cell library. I imported a verilog netlist beside the LEF file in encounter, placed & routed the design, and finally generated the SDF file.

After opening the SDF in an editor I only see delay information for the interconnects. I don't understand why the gates input to output path delays are missing in the generated SDF file.

I would appreciate if somebody could tell me what I'm missing.

Thanks 

 

Parents

  • I checked with one of our library characterization tool experts and here is what I found out for you. Hope this helps.

    To create a Liberty timing library characterization needs -
     
    1. Transistor level netlist for the cell (Spice netlist)
    2. Transistor models (Spice model)
    3. A command file that tells the tool (ELC, Liberate) what and how to characterize. E.g., what
    circuit simulator you want to use (e.g., Hspice, Spectre), what timing and cap index etc.
     
    The Cadence library characterizer can be Encounter Library Characterizer (ELC) or Liberate.

Reply

  • I checked with one of our library characterization tool experts and here is what I found out for you. Hope this helps.

    To create a Liberty timing library characterization needs -
     
    1. Transistor level netlist for the cell (Spice netlist)
    2. Transistor models (Spice model)
    3. A command file that tells the tool (ELC, Liberate) what and how to characterize. E.g., what
    circuit simulator you want to use (e.g., Hspice, Spectre), what timing and cap index etc.
     
    The Cadence library characterizer can be Encounter Library Characterizer (ELC) or Liberate.

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