I'm using layer 3 and layer 4 for the power routing, so there are many vias through layer 3, layer 2 to layer 1.
Then there are some short circuit problems when some signals pass through the vias. Is there any option to avoid this kind of problems? Can't the tool detect these short problems and avoid these?
Two possible solutions
A) pre-place filler cells under all of your vertical power stripes to prevent standard cell placement in the power via stack shadow.
B) reduce the size of the power via stack with addStripe option -max_via_size