I'm using layer 3 and layer 4 for the power routing, so there are many vias through layer 3, layer 2 to layer 1.
Then there are some short circuit problems when some signals pass through the vias. Is there any option to avoid this kind of problems? Can't the tool detect these short problems and avoid these?
Without seeing the power route floorplan it is difficult to tell what the problem is but if the router is creating shorts through power vias it sounds like your design is too congested by the power vias. Could you post a picture of your floorplan showing the power routing?
I have posted part of the power routing.
Could I control the power vias by configuring the tool? or I just remove the vias that cause the short circuit?
Two possible solutions
A) pre-place filler cells under all of your vertical power stripes to prevent standard cell placement in the power via stack shadow.
B) reduce the size of the power via stack with addStripe option -max_via_size
Actually I have already put the place blockage under those stripes, so there isn't any standard cell under the strips.
The problem is the routing lines passing through the vias, which will cause the short circuit.
I think I can just remove the related vias, how do you think about that?
If there is any active circuitry on the cell row I would be very wary of deleting either of the nearest power via stacks completely. That may lead to static and / or dynamic IR drop issues, local voltages lower than your worst case timing library will model correctly. Finding IR drop problems at the last minute before tape out is no fun whatsoever, believe me. You can use the "editPowerVia" command to selectively reduce the array size of the power via stacks in the problem areas.For example, reduce the via stack array from a 6x1 array to a 4x1 in localized problem areas.Or if you know the "full sized" power via stack array is over kill for your technology / library / circuit you can globally shrink them from the start with the addStripe option -max_via_size.Shawn